Information Theoretic Evaluation of Side-Channel Resistant Logic Styles

ion Layers logic transistor layout physical L L L L e.g. Hamming weight assumption e.g. single gates simulation e.g. post place and route simulations e.g. actual measurements implementation protocol algorithm Circuit abstraction levels ⇔ useful for a simulation based approach Limit due to : Going deeper in the abstraction levels ⇒ different amount of information due to more realistic scenarios. Physical level is better but simulation approach not meaningless.